File netnames.txt, 19/10/95.

HP-PC Interface Net names and use
---------------------------------


RDB[17:0]	Ram Data Bus, Xblox Bus 
BRMO[17:0]	Build Register Multiplexer output, Xblox Bus 
IMBQ[15:0]	Input mailbox outputs, Xblox Bus 
IMBQH[7:0]	Input mailbox outputs, high byte, Xblox Bus 
IMBQL[7:0]	Input mailbox outputs, low byte, Xblox Bus 
BRIM[7:0]	Build Register Input side multiplexer outputs, Xblox Bus 
BRT[1:0]	Build Register Tag inputs, Xblox Bus
BRQ[17:0]	Build Register Outputs, Xblox bus
BRQL[17:0]	Build Register Outputs, Bits 0-7, Xblox bus
BRQH[17:0]	Build Register Outputs, Bits 8-15, Xblox bus
BRQT[17:0]	Build Register Outputs, Bits 16-17 (Tag), Xblox bus
OMBQ[17:0]	Output mailbox outputs, Xblox Bus
CD[7:0]		Command Data, Xblox Bus
ICR[7:0]	Input Command Register outputs, Xblox Bus
BRC[3:0]	Bios Report codes to HP, Xblox Bus
RBRC[3:0]	Registered Bios Report codes to HP, Xblox Bus
PCS[7:0]	Status lines to PC BUS, Xblox Bus
PCDI[15:0]	PC Data Bus Input direction, Xblox Bus
PCDIL[7:0]	PC Data Bus Input direction, Low Byte, Xblox Bus
PCDO[15:0]	PC Data Bus Output direction, Xblox Bus
MA[0:14]	FIFO Address Multiplexer Output lines, Xblox bus
XMASEL[0:0]	FIFO Address Multiplexer select line, Xblox bus
FRC[14:0]	FIFO Read Counter Outputs, Xblox bus
FWC[14:0]	FIFO Write Counter Outputs, Xblox bus
FRC[14:0]	FIFO Status Counter Outputs, Xblox bus
PCHPSF[3:0]	PC to HP Status Bus Force lines, Xblox Bus 
PCSGND[3:0]	PC STatus Bus Force line to GND, Xblox Bus 
SMPQ[15:0]	State Machine Prom Outputs, Xblox Bus 
SMCSQ[15:0]	State Machine Control Signals Output from Register, Xblox Bus 
SMADD[5:0]	State Machine Current Prom Address, Xblox Bus, Xblox Bus 
SMSTART[5:0]	State Machine Address For Execution Cyvle Start, Xblox Bus
SMP[2:0]	State Machine Parameters, Viewlogic Bus 
MST[7:0]	Machine state (used in replacement of Prom)
COM[7:0]	Command in operation (used in replacement of Prom)

BIORL		Buffered I/O Read (Active Low, Pad Name)
IORL		Buffered I/O Read (Active Low, Internal Name)
BIOWL		Buffered I/O Write (Active Low, Pad name)
IOWL		Buffered I/O Write (Active Low, Internal name)
XPCA1		PC Address line A1 (Pad name)
PCA1		PC Address line A1 (Internal name)
XPCA2		PC Address line A2 (Pad name)
PCA2		PC Address line A2 (Internal name)
GSR		Global Set/Reset
LDC		Low during configure
ECK		External Clock (pad name)
CK		Internal Clock, distributed by Primary Global Buffer
		  for low skew
BROMS		Build Register Output Side Multiplexer Select
BRIMS		Build Register Input Side Multiplexer Select
BRCE0		Build Register Clock Enable 0 (Low Byte)
BRCE1		Build Register Clock Enable 1 (High Byte & Tag)
CR		Command Reset
PCCR		PC Command Reset
BRTE		Bios Report Code Transfer Enable
FRR		Fifo Reset Request
SRR		Status Report Request
PCOEL		Output enable (act. low) for the buffers driving
		  the external PC Bus
RDBOEL		Output enable (act. low) for the buffers driving
		  the external Ram Data Bus
OMBCE		Output Mailbox Clock Enable
OMBF		Output Mail Box Full
OMBR		Output Mail Box Read
OMBRD		Output Mail Box Read Delayed
OMBC		Output Mail Box status FF Clear
SPCHPF		Set PC to HP (ie: status) Flag line
XPCHPC		PC to HP (ie: status) Command line (Pad name)
PCHPC		PC to HP (ie: status) Command line (Internal name) 
XPCHPF		PC to HP (ie: status) Flag line (Pad name)
PCHPF		PC to HP (ie: status) Flag line (Internal name)
XHPPCC		HP to PC (ie: Data) Command line (Pad name)
HPPCC		HP to PC (ie: Data) Command line (Internal name)
XHPPCF		HP to PC (ie: Data) Flag line
		  (Pad name, buffered inverted version of IMBF)
IMBF		Input Mailbox Full
IMBFR		Input Mailbox Full Reset
RPCS		Read PC Status
RPCSD		Read PC Status Delayed
HFRR		HP Fifo Reset Request
RHFRR		Registered HP Fifo Reset Request (Equivalent to PCS4)
FR		Fifo Reset
RPCFR		Registered PC Fifo Reset
FRRC		Fifo Reset Register Clear
FF		Fifo Full
RFF		Registered Fifo Full
FHF		Fifo Half Full
RFHF		Registered Fifo Half Full
FE		Fifo Empty
RFE		Registered Fifo Empty
MASEL		FIFO Address Multiplexer select line
FRCCE		FIFO Read Counter Clock Enable
FWCCE		FIFO Write Counter Clock Enable
FSCCE		FIFO Status Counter Clock Enable
FSCUP		FIFO Status Counter Up/-Down
XSELL		Xilinx Address Range select (Pad name)
SELL		Xilinx Address Range select (Internal name)
HWORD		High/-Low Data Word in Output Mailbox
DWORD		Data/-Command Word in Output Mailbox
HBYTE		Byte 1 or 3 is in Input Mailbox if the word is a data word
		  otherwise the bit is don't care.
TAG[1:0]	0X -> Command Word, 10 -> Low Data Word, 11 -> High Data Word		
CWL		Command Write (Active Low)
PCHPLE		PC->HP Status Latch Enable (Internal name)
HPPCOE		HP->PC Data Buffer Enable (Internal name)
XPCHPLE		PC->HP Status Latch Enable (Pad name)
XHPPCOEL	HP->PC Data Buffer Enable Active Low (Pad name)
RCEL		RAM Chip Enable Active Low (Internal name)
WEL		RAM Write Enable Active Low (Internal name)
XRCEL		RAM Chip Enable Active Low (Pad name)
XWEL		RAM Write Enable Active Low (Pad name)
XBUSY		Active from the writing of the command until the HP has
		read the status
XACT		Xilinx is Busy executing a PC command (internal)