File ctrlnet.txt, 19/10/95. HP-PC Interface Control Net names and use ----------------------------------------- Early Inputs To Control State Machine ===================================== FRR Fifo Reset Request SRR Status Report Request SPCHPF Set PC to HP (ie: status) Flag line IMBF Input Mailbox Full OMBF Output Mail Box Full HBYTE Byte 1 or 3 is in Input Mailbox if the word is a data word otherwise the bit is don't care. TAG[1:0] 0X -> Command Word, 10 -> Low Data Word, 11 -> High Data Word FF Fifo Full FE Fifo Empty Late Inputs To Control State Machine ==================================== SMP[2:0] State Machine Parameters Coding : SMP2 SMP1 SMP0 FUNCTION --------------------------------------------------------------- 1 1 1 Reset Fifo 1 1 0 Send Bios Report Code 1 0 1 Read FIFO to OMB 1 0 0 HP1000 data transfer 0 1 1 Not Used 0 1 0 Not Used 0 0 1 Not Used 0 0 0 IDLE Outputs From Control State Machine ================================== BROMS Build Register Output Side Multiplexer Select BRIMS Build Register Input Side Multiplexer Select BRCE0 Build Register Clock Enable 0 (Low Byte) BRCE1 Build Register Clock Enable 1 (High Byte & Tag) CR Command Reset PCCR PC Command Reset BRTE Bios Report Code Transfer Enable MASEL FIFO Address Multiplexer select line FRCCE FIFO Read Counter Clock Enable FWCCE FIFO Write Counter Clock Enable FSCCE FIFO Status Counter Clock Enable. This line is created by ORing FRCCE & FWCCE at the Prom Output since Writing and Reading the Fifo modifies the Fifo Status Counter. FSCUP FIFO Status Counter Up/-Down RDBOEL Output enable (act. low) for the buffers driving the external Ram Data Bus OMBCE Output Mailbox Clock Enable IMBRR Input Mailbox Ready Reset FR Fifo Reset. This line is created by ANDing FRCCE & FWCCE at the Prom Output since Writing and Reading the Fifo at the same time is meaningless. PCHPLE PC->HP Status Latch Enable HPPCOE HP->PC Data Buffer Enable RCEL RAM Chip Enable Active Low WEL RAM Write Enable Active Low