Xilinx Hot Line : France 00 33 1 34 63 01 00 Vincent Tabourier / Raymondeau

XACT

- FJKRSE does not simulate if S, K and CE are left open.
- Xblox PROM is not correctly implemented even if it lays on top level sheet.
- FORCE primitive asks for bounds if UBIN is used instead of BIT.
- BIT is not equivalent to UBIN for the software while this is stated otherwise in
  the Xblox manual
- OUTSLICE is not equivalent to SLICE. When OUTSLICE is put between BIDIR_IO and
  DATA_REG primitives and Style=ILD is specified on the register, the OUTSLICE
  prevents moving the registers in the IO pads while SLICE succeeds.

Viellogic PROseries

- "View Prowave annotation OFF" does not stop displaying net values.